(1) Field of the Invention
The present invention relates to a semiconductor device used in, for example, an optical communication system and, more particularly, to a semiconductor photodetector and a method for manufacturing the same, suitable for use as an avalanche photo diode (APD) having a mesa structure advantageous in reducing capacitance.
(2) Description of Related Art
Recently, following a considerable increase in demand for communication due to the prevalence of the Internet, a higher-speed optical communication system is demanded. For example, a photodetective device used in an optical communication system is required to provide a data transmission rate equal to or greater than 10 Gbit/s.
For example, as a photodetective device capable of high-speed operation, an avalanche photodiode (APD) having a multiplication mechanism in its device is known.
Currently, in an optical communication system, an APD having a planar structure is mainly put into production. This is because the side of a pn junction as an operation portion is covered with a semiconductor layer and low dark current can be realized, therefore, the reliability of the device is ensured and lower noise characteristics can be realized.
As shown in FIG. 23 for example, a planar APD comprises a light absorbing layer 53 for absorbing light incident from the backside of a semiconductor substrate 51 and converting it into an electric signal and an avalanche multiplication layer 55 for multiplying an electric signal and has a structure in which a p-type semiconductor layer 56 and an n-type semiconductor layer 52 sandwich the light absorbing layer 53 and the avalanche multiplication layer 55.
In other words, as shown in FIG. 23, a planar APD has a structure, for example, in which the n-InP buffer layer 52 (Si dope; thickness 2 μm; concentration 2×1018 cm−3; n-type semiconductor layer), the i-InGaAs light absorbing layer 53 (undope; thickness 1 μm), an n-InP electric field buffer layer 54 (Si dope; thickness 50 nm; n-type semiconductor layer), the i-InP avalanche multiplication layer 55 (undope; thickness 100 nm), and the p-InP layer 56 (Zn dope; thickness 1 μm; concentration 1×1018 cm−3; p-type semiconductor layer) are stacked sequentially on the n-InP substrate 51 (Si dope; concentration 2×1018 cm−3; n-type semiconductor layer).
Then, on the p-InP layer 56, a p-side contact electrode 57 is further formed and a p-side electrode pad 58 is formed so as to cover the p-side contact electrode 57. On the n-InP buffer layer 52, an n-side contact electrode 59 is formed and an n-side electrode pad 60 is formed so as to cover the n-side contact electrode 59. Further, a passivation film 61 is formed so as to cover the surface. An anti-reflection film 62 is formed on the backside of the substrate. The p-side electrode pad 58 and the n-side electrode pad 60 are connected to a fixing substrate by, for example, flip-chip bonding.
While the thickness of the light absorbing layer 53 is reduced in order to enable high-speed operation, light having transmitted through the light absorbing layer 53 without being absorbed is reflected by the backside of the p-side electrode pad 58 such that it is again incident into the light absorbing layer 53, substantially doubling the thickness of the light absorbing layer 53 for incident light and thus improvement toward higher efficiency can be realized.
In order to improve the high-speed response characteristics and the low noise characteristics, a structure is employed, in which the light absorbing layer 53 and the avalanche multiplication layer 55 are separated, and thereby as shown in FIG. 24(B), for example, the electric field intensity in the avalanche multiplication layer 55 is increased and the electric field intensity in the light absorbing layer 53 is reduced during the period of APD operation. In other words, as shown in FIG. 24(A), for example, the film thickness and the impurity concentration of each of the p-type semiconductor layer 56, the avalanche multiplication layer 55, the electric field buffer layer 54, the light absorbing layer 53, and the n-type semiconductor layer 52 are set such that such an electric field intensity distribution in the device is obtained.
Generally, in the planar APD, the p-InP layer 56 is formed by diffusing p-type impurity (for example, Zn) into the i-InP multiplication layer 55 by carrying out selective diffusion. Due to this, such an impurity concentration as shown in FIG. 24(A) described above is realized. Because of this, by controlling the depth of diffusion of the p-type impurity, the film thicknesses of the p-InP layer 56 and the i-InP multiplication layer 55 are controlled. In an APD having a mesa structure, which will be described later, the p-InP layer 56 and the i-InP multiplication layer 55 are formed by changing the dopant during the period of growth and such a concentration distribution as shown in FIG. 24(A) described above is realized.
Technical documents about such a planar APD include, for example, Y. Kito et al. “High-Speed Flip-Chip InP/InGaAs Avalanche Photodiode with Ultra low Capacitance and Large Gain-Bandwidth Products” IEEE Photon. Technol. Lett. 3 1115-1116 (1991).
Currently, it has become necessary to reduce device capacitance in order to further increase the operation speed.
It is effective to employ a mesa structure as a pn junction structure in order to realize reduction in capacitance of the device. For example, when an APD has a data transmission rate (rate of information throughput) of 10 Gbit/s, the junction capacitance can be reduced by about 50% by employing a mesa structure.
The reason is as follows. The planar APD has a structure in which the p-InP layer 56 is buried in the i-InP multiplication layer 55 in contact with the n-InP electric field buffer layer 54, as described above (refer to FIG. 23), therefore, a pn junction is formed not only on the lower side face of the p-InP layer 56 but also on the lateral side face of the p-InP layer 56 and thereby a depletion layer is formed and the capacitance of this portion (fringe capacitance) is added to the junction capacitance, however, in the mesa APD, the pn junction is formed only on the lower side face of the p-InP layer 56 and therefore the depletion layer formed by this has a parallel plate shape and the fringe capacitance is not added to the junction capacitance.
Particularly, the proportion constituted by the fringe capacitance in the device capacitance increases as the device area decreases. Therefore, as the device area is reduced in an attempt to aim at higher-speed operation, the capacitance reduction effect by employing a mesa structure becomes more prominent.
Because of this, recently, the research and development of the mesa APD as a photodetective device having the high-speed response characteristics are being conducted intensively. It has become possible for the mesa APD to obtain sufficient frequency response characteristics (high-speed response characteristics) for the demand for a high transmission rate of 10 Gbit/s or higher.
The technologies about the structure of a mesa APD are disclosed in, for example, Japanese Patent Laid-Open (Kokai) HEI 8-181349, Japanese Patent Laid-Open (Kokai) HEI 11-354827, Japanese Patent Laid-Open (Kokai) 2001-196623, etc.